1. Field of the Invention
The present invention relates to a semiconductor memory protocol, and more particularly, to a device for delaying a clock signal using a ring delay.
2. Discussion of the Background Art
In general, a clock signal is required for reading a data in a memory, which is provided externally. However, the clock received from outside of a chip is delayed for a certain time due to actual characteristics of pins or an internal circuit.
FIG. 1 illustrates a data read timing diagram for a background art SDRAM.
When reading a data from the chip using the external clock signal, a time delay is occurred naturally at a moment when an external clock signal is provided to the chip, and, alikely, a time delay is also occurred when an output buffer is driven for reading the data. Thus, there are cases when the data can not be read. That is, after having a certain time period of TAC (Time Access from Clock) at a rising edge of the clock signal, the data is taken from the system at a moment of the next rising edge (a data strobe time of the system). Despite a data output time to the clock should be stable regardless of a frequency, TAC.gtoreq.tCLK is occurred if the frequency is high, which does not allow the intended data reading. Therefore, in order to make TAC.ltoreq.tCLK, it is necessary to pull a timing of the external clock signal provided to inside of the chip forward. The time delay is an important parameter for reading data in the memory, and particularly, a clock access time is an important parameter for a fast SDRAM. The clock skew due to the propagation delay through clock buffer and driver must be compensated for fast clock access. Phase locked loop (PLL) and delay locked loop (DLL) have been widely used to compensate the clock skew. However, for exact locking, they require more than 50 clock cycles, which increase the standby current.
Such a background art synchronous mirror delay line will be explained with reference to the attached drawing. FIG. 2 illustrates a system of the background art synchronous mirror delay line.
When an external clock is received in a chip, the clock signal is delayed for a certain time due to the foregoing reasons, naturally. And, there is a time delay at a moment an output buffer is driven for reading data from a memory, naturally. Accordingly, though they are not present in the circuit actually, buffers 1 and 2 are provided in FIG. 2 for explaining the naturally occurring time delays. d1 and d2 are the time delays, eCLK is an external clock signal, and rCLK is a clock signal received inside of the chip. The background art synchronous mirror delay line is provided with a delay 3 for delaying an external clock signal for the d1+d2, a TDC (Time to Digital Converter) 4 synchronous to the internal clock signal rCLK for digitizing a time period of the clock signal delayed in the delay 3, and a flipflop part 6 for latching signals from the TDC 4 and the DTC 5 in response to the internal clock signal rCLK.
Operation of the background art synchronous mirror delay line will be explained. FIG. 3 illustrates a timing diagram of a background art TDC and a clock cycle, and FIG. 4 illustrates waveforms of different parts in the background art synchronous mirror delay line.
The external clock signal eCLK is received in the chip with a certain time d1 delay as internal clock signal rCLK (see rCLK in FIG. 4). And, the internal clock signal rCLK delayed for a certain time is provided to the TDC 4 through the delay 3. In this instance, the clock signal at "A" point shown in FIGS. 2 and 4 after the delay 3 is provided to the TDC 4 after being delayed for d1+d2 from the clock signal rCLK. The TDC 4 measures tCLK-(d1+d2) and converts into a digital delay count. That is, each flipflop F/F in the flipflop part 6 latches a signal from one of unit delays tpd in the TDC 4, so that a "high" clock is latched at only one of the plurality of flipflops F/F at a moment when the internal clock is at a rising edge. The TDC 4 uses this in measuring the tCLK-(d1+d2) and converts the tCLK-(d1+d2) into a digital delay count (see FIG. 4 waveform B). And, the DTC 5 receives the measured digital delay count as a control signal and delays the clock signal received for locking an output of the clock driver to the external clock as much as tCLK-(d1+d2), again (see FIG. 4 waveform C). Therefore, the clock signal driving the output buffer at the end is delayed for the naturally delayed time period d2 (see FIG. 4 waveform liCLK). Thus, a timing of an external clock signal provided to the chip is pulled forward. In the meanwhile, as shown in FIG. 3, a time resolution of the DTC 5 is the same with the time delay of a unit delay tpd that determines a jitter of the internal clock. That is, as shown in FIG. 3, a condition as Ntpd.gtoreq.tCLK.gtoreq.d1+d2 (time delays in the delay part)+(F/F set time) provides a range of operation for locking the clock. The tpd should be small for reducing the jitter, and N should be small when the range of operation is great. If the tpd is 100 ps, the N should be equal to or greater than 200 for locking the 50 MHz external clock. As the DTC 5 requires unit delays the same as a number of the TDC 4, a total number of the unit delays of delay lines is 2N.
The aforementioned background art synchronous mirror delay line has the following problems.
That is, since the tpd should be small for reducing jitter, a number N of tpd should be great for a greater range of operation, and the DTC 5 requires the same number of unit delays as the TDC 4, which requires a 2N number of total unit delays in the delay line as well as an N number of flipflops F/F for processing data. Thus, the delay line consumes much silicon area.